PCIe Software Engineer
Arista Networks
Software Engineering
Santa Clara, CA, USA
USD 123k-191k / year + Equity
Company Description
Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges.
At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation.
Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do.
Job Description
Who You'll Work With
Operating right where hardware meets software, the Platform team builds the foundation for our networking ASICs and supporting infrastructure. PCIe software engineers write the code that manages high speed communication between hardware components in our switches. We work with hardware, diagnostics, and software engineers to maximize bandwidth and improve reliability on the PCIe links.
What You'll Do
As part of this team, you’ll work on projects like:
- Bringing up pcie links on new hardware designs
- Tuning pcie parameters on root ports, bridges, and end points
- Modifying the linux pci drivers and virtual memory allocation
- Using AER and DPC to improve error visibility and resiliency
- Developing userspace software that mediate between networking ASICs, FPGAs, and PCIe bridges.
- Measuring hardware read and write performance
- Develop automated tests using C, C++ and Python to validate your features.
Qualifications
- Strong engineering and Computer Science fundamentals.
- 3+ years fluency in C or C++. Python experience an added bonus.
- Solid understanding of PCIe hardware and software drivers
- PCIe state machine, ltssm, tlp, credit flow control knowledge a plus
- Experience with PCIe switches
- Significant hands-on experience diagnosing problems, troubleshooting issues, and fixing bugs in low-level firmware
If you’re passionate about performance optimizations and enjoy working at the hardware/software boundary, the Platform team is a perfect choice!
Compensation Information
The new hire base pay for this role has a pay range of $123,000 to $191,000.
Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location.
The pay range provided reflects base pay only and in addition certain roles may also be eligible for discretionary Arista bonuses and equity. Employees in Sales roles are eligible to participate in Arista’s Sales Incentive Plan, which pays commissions calculated as a percentage of eligible sales. US-based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location
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Additional Information
Arista Networks is an equal opportunity employer. Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law. All your information will be kept confidential according to EEO guidelines.